Cross-bidge Kelvin resistor (CBKR) structures for measurement of low contact resistances

A convenient test structure for measurement of the specific contact resistance (ρc) of metal-semiconductor junctions is the CBKR structure. During last few decades the parasitic factors which may strongly affect the measurements accuracy for ρc < 10-6 Ω • cm2 have been sufficiently discussed and the minimum of the ρc to be measured using CBKR structures was estimated. We fabricated a set of CBKR structures with different geometries to confirm this limit experimentally. These structures were manufactured for metal-to-metal contacts. It was found that the extracted CBKR values were determined by dimensions of the two-metal stack in the contact area and sheet resistances of the metals used. \ud Index Terms—Contact resistance, cross-bridge Kelvin resistor (CBKR), sheet resistance, test structures, metal, silico

An Initial study on The Reliability of Power Semiconductor Devices

An initial literature study combined with some basic comparative simulations has been performed on different electricfield modulation techniques and the subsequent reliability issues are reported for power semiconductor devices. An explanation of the most important power device metrics such as the offstate breakdown (BV) and specific on-resistance (RON) will be given, followed by a short overview of some of the electrostatic techniques (fieldplates, RESURF e.g. [1]) used to suppress peak electric fields. Furthermore it will be addressed that the high current operation of these devices results in shifting electric field peaks (Kirk effect [2], [3]) and as such different avalanche behavior, resulting in (gate oxide) reliability issues unlike those of conventional CMOS

Design optimization of field-plate assisted RESURF devices

A mathematical model for optimizing the 2-D potential distribution in the drift region of field-plate (FP)-assisted RESURF devices (Fig. 1) is presented. The proposed model extends earlier work [1-2] by including top-bottom dielectric asymmetry (typical in SOI devices [3]), non-zero field plate potentials VFP and grading of design parameters other than drift region doping. This generally-applicable, TCAD-verified [4], model provides a guideline for optimizing the drain extension in a wide range of FP-assisted RESURF devices

Field plate assisted resistance reduction in a semiconductor device

intentionally left blan

Interface trap density estimation in FinFETs using the gm/ID Method in the subthreshold regime

In this paper, we show that the subthreshold current-voltage characteristic can be used for estimating the interface trap density as a function of the energy in fully depleted symmetric metal-oxide-semiconductor devices with a minimum amount of modeling. The method is analyzed using TCAD simulations, and illustrated with the measurements on n-type silicon-on-insulator FinFETs. The results indicate that the trap density can be extracted between ~0.65 and 0.90 eV. This range is limited by resolution issues at the lowest current levels, and by the transition from subthreshold to saturation behavior at the high current levels

Impact of interface charge on the electrostatics of field-plate assisted RESURF devices

A systematic study on the effects of arbitrary parasitic charge profiles, such as trapped or fixed charge, on the 2-D potential distribution in the drain extension of reverse-biased field-plate-assisted reduced surface field (RESURF) devices is presented. Using TCAD device simulations and analytical means, the significance of the so-called characteristic or natural length λ is highlighted with respect to the potential distribution and related phenomena in both ideal (virgin) and nonideal (degraded) extensions. Subsequently, a novel and easy-to-use charge-response method is introduced that enables calculation of the potential distribution for an arbitrary parasitic charge profile once the peak potential and lateral fall-off (∝λ) caused by a single unit charge has been determined. This can be used for optimizing and predicting the performance, also after hot carrier injection, of RESURF power devices

Extraction of the electric field in field plate assisted RESURF devices

It has previously been reported that the lateral electric field (Ex) in the drain extension of thin SOI HV (700V) field plate assisted RESURF devices can be extracted from their ID-VD characteristics in the subthreshold regime. In this work the prerequisites for valid field extraction and the (voltage) range of validity are established for linearly graded drain extension based RESURF devices through a combination of analytical calculations and TCAD device modeling. It is shown that the most important condition for field extraction is that an increment dVDS should not affect the lateral field at the already depleted zone. This unique condition is found to be met in the drain extension at distances larger than a specific length (5.3_) governed by the drain extension silicon and oxide thicknesses. For realistic device parameters the method is shown to hold for devices with a BVDS of _ 150V and higher

Physics-based stability analysis of MOS transistors

In this work, a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal–oxide–semiconductor (MOS) transistors. The proposed model can be easily interfaced with a circuit or device simulator to perform a failure analysis, making it particularly useful for power transistors. Furthermore, it allows mapping the failure points on a three-dimensional (3D) space defined by the gate-width normalized drain current, drain voltage and junction temperature. This leads to the definition of the Safe Operating Volume (SOV), a powerful frame work for making failure predictions and determining the main root of instability (electrical, thermal or electro-thermal) in different bias and operating conditions. A comparison between the modeled and the measured SOV of silicon-on-insulator (SOI) LDMOS transistors is reported to support the validity of the proposed stability analysis

Identifying failure mechanisms in LDMOS transistors by analytical stability analysis

In this work, analytical stability equations are derived and combined with a physics-based model of an LDMOS transistor in order to identify the primary cause of failure in different operating and bias conditions. It is found that there is a gradual boundary between an electrical failure region at high drain voltage and a thermal failure region at high junction temperature. The theoretical results are mapped onto a 3D space comprising gate-width normalized drain current, drain voltage and junction temperature, allowing an immediate visualization of the different failure mechanisms. The validity of the proposed analysis is supported by measurements of the safe operating limits of silicon-on-insulator (SOI) LDMOS transistors

On the degradation of field-plate assisted RESURF power devices

Hot-carrier degradation phenomena in field-plate assisted reduced surface field (RESURF) devices caused by high voltage off- and on-state stressing have been investigated. The device I-V characteristics are analyzed and modeled in detail. It is shown that via noninvasive low-voltage leakage characterization the surface generation velocity profiles after (high-voltage) stress can be extracted, enabling I-V degradation predictions across wide temperature ranges